The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventor hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Iterative codes have found wide-spread application in areas such as magnetic recording and data communications. Such codes are often used with a detector (e.g., a Viterbi detector) to provide a degree of error correction when detecting and decoding received or recorded data. One example of an iterative code is a low-density parity-check (LDPC) code.
There exist a variety of techniques to decode iterative codes (such as LDPC codes). Different ones of those techniques may have different performance characteristics, such as complexity, power profile, hardware requirements, convergence profile (i.e., how many iterations are needed to converge on a decoded codeword), and reliability (i.e., how likely it is that a codeword will be successfully decoded). These performance characteristics are often conflicting. For example, it is desirable to have lower power consumption and smaller hardware size, while at the same time having better reliability and higher throughput. It may be difficult to achieve all of those goals using a single decoding technique. Instead, different decoding techniques (or variations of a specific technique) may be needed to achieve different ones of those goals. Moreover, different input data patterns may result in different performance for same technique or, put another way, achieving the same performance for different input data patterns may require use of different techniques.